At present, each floating-gate transistor used for storage on a solid state drive (SSD) can store two or three bits. The bits stored in each floating-gate transistor are separately distributed on different pages. Therefore, pages in each block are classified into two or three different types according to storage locations in floating-gate transistors.
Using multi-level cell storage (MLC) as an example, two bits of a floating-gate transistor of the multi-level cell storage are respectively referred to as a least significant bit (LSB) and a most significant bit (MSB). Therefore, in each block, pages on which different bits in floating-gate transistors are separately located are classified into two types: an LSB page (for storing the LSB of the floating-gate transistor; the LSB page may also be referred to as a lower page and in this application, the LSB page is used uniformly) and an MSB page (for storing the MSB of the floating-gate transistor; the MSB page may also be referred to as an upper page and in this application, the MSB page is used uniformly). On a basis that data of corresponding bits of the LSB page and the MSB page is stored in a same floating-gate transistor, the LSB page and the MSB page belong to one group of shared pages. Specifically, Table 1 describes shared pages in a block of an MLC of a vendor.
TABLE 1LSB pageMSB page 02 14 36 58 710 912 1114. . .. . .. . .. . .241244243246245248247250249252251254253255
When data is being written, LSBs may need to be written before MSBs. Therefore, data can be written into a corresponding MSB page only after an entire LSB page is full. However, writing data into the MSB page causes interference to data that has been written into the LSB page before. Using the foregoing MLC of the vendor as an example, Table 2 describes interference data that is obtained during data writing according to an experiment.
TABLE 2PagePage 0Page 1Page 2Page 3Page 4Page 5Page 6Page 7Page 8Page 000125 105 53463Page 12115035896Page 20000000Page 3000296 193 25 Page 4171514 15 16 Page 5000270 Page 6000Page 710Page 80
The foregoing Table 2 describes interference on vertical pages when data is written into horizontal pages. It can be known from the foregoing Table 2 that, when data is being written into an MSB page, a relatively severe error correcting code (ECC) error or uncorrectable ECC error (UNC) may occur on a shared LSB page of the MSB page and on a shared LSB page of an adjacent MSB page. As shown in Table 2, underlined data has relatively severe errors.
Likewise, for a storage device whose floating-gate transistor stores more bits, for example, a storage device whose floating-gate transistor stores three bits, which means that a group of shared pages includes an LSB page, a middle significant bit (CSB) page, and an MSB page, writing into an upper page also causes write interference to a lower page.
Therefore, if data is read from a lower page when the lower page is subject to write interference, a data read error occurs. An existing common solution to this problem is to improve an ECC error correction capability of an SSD, so that a controller of the storage device corrects a data read error by using an ECC when reading data from a page that is subject to write interference. However, improving the ECC error correction capability requires support from the controller. In addition, when space of a spare area provided by the storage device for ECCs is given, it is difficult to further improve the ECC error correction capability. Therefore, a read error still occurs during data reading due to write interference.